DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1006

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-TL1)
19.3.5
The Timer is 16 bits and supports several source clocks. A pre-scale counter can be used to reduce
the speed of the clock. It also supports three Compare Match Registers (TCMR2, TCMR1,
TCMR0). The address map is as follows.
Important: These registers can only be accessed in Word size (16-bit).
(1)
The Time Trigger Control Register0 is a 16-bit read/write register and provides functions to
control the operation of the Timer. When operating in Time Trigger Mode, please refer to section
19.4.3 (1), Time Triggered Transmission.
• TTCR0 (Address = H'080)
Rev. 3.00 Sep. 28, 2009 Page 974 of 1650
REJ09B0313-0300
Description
Timer Trigger Control Register 0
Cycle Maximum/Tx-Enable
Window Register
Reference Trigger Offset Register
Timer Status Register
Cycle Counter Register
Timer Counter Register
Cycle Time Register
Reference Mark Register
Timer Compare Match Register 0
Timer Compare Match Register 1
Timer Compare Match Register 2
Tx-Trigger Time Selection Register 0A4
Initial value:
Time Trigger Control Register0 (TTCR0)
R/W:
Bit:
Timer Registers
TCR15 TCR14 TCR13 TCR12 TCR11
R/W
15
0
R/W
14
0
R/W
13
0
Figure 19.12 RCAN-TL1 Timer registers
R/W
12
0
R/W
11
0
Address
080
084
086
088
08A
08C
090
094
098
09C
0A0
TCR10
R/W
10
0
R
9
0
-
R
8
0
-
R
7
0
Name
TTCR0
CMAX_TEW
RFTROFF
TSR
CCR
TCNTR
CYCTR
RFMK
TCMR0
TCMR1
TCMR2
TTTSEL
-
TCR6 TPSC5
R/W
6
0
R/W
5
0
TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
R/W
4
0
Access Size (bits)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
Word (16)
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0