DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1156

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 23 USB 2.0 Host/Function Module (USB)
Note: Only reading 0 and writing 1 are valid.
23.3.10 Transaction Counter Registers (D0FIFOTRN, D1FIFOTRN)
D0FIFOTRN and D1FIFOTRN are registers that are used to set the number of DMA transfer
transactions and read the number of transactions.
These registers are initialized by a power-on reset and a software reset.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1124 of 1650
REJ09B0313-0300
Bit
13
12 to 0
Bit
15 to 0
R/W:
Bit:
R/W
Bit Name
SBUSY
Bit Name
TRNCNT
[15:0]
15
0
R/W
14
0
R/W
13
0
Initial
Value
0
All 0
Initial
Value
H'0000
R/W
12
0
R/W
11
0
R/W
R/W
R
R/W
R/W
R/W
10
0
R/W
9
0
Description
SIE Buffer Busy
0: SIE is not being accessed.
1: SIE is being accessed.
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Transaction Counter
These bits are valid when data is being read from the
buffer memory.
The number of transactions that is being counted can
be read when the TRENB bit in DnFIFOSEL is set to
1. If the TRENB bit is cleared to 0, the set number of
transactions can be read.
W: Sets the number of DMA transfer transactions
R: Reads the number of transactions
TRNCNT[15:0]
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0

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