DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 288

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 9 Bus State Controller (BSC)
Rev. 3.00 Sep. 28, 2009 Page 256 of 1650
REJ09B0313-0300
Bit
12, 11
10 to 7
6
Bit Name
SW[1:0]
WR[3:0]
WM
Initial
Value
00
1010
0
R/W
R/W
R/W
R/W
Description
Number of Delay Cycles from Address, CS0 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored

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