DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 530

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.11 Timer Counter (TCNT)
The TCNT counters are 16-bit readable/writable counters. The MTU2 has five TCNT counters,
one each for channels 0 to 4.
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
Initial value:
11.3.12 Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers. The MTU2 has eighteen TGR registers,
six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers.
TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers.
TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD.
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the
TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for
operation as a buffer register. TGR buffer register combination is TGRE and TGRF.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 498 of 1650
REJ09B0313-0300
Note:
Note:
R/W:
R/W:
Bit:
Bit:
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits.
TGR registers are initialized to H'FFFF.
R/W
R/W
15
15
0
1
R/W
R/W
14
14
0
1
R/W
R/W
13
13
0
1
R/W
R/W
12
12
0
1
R/W
R/W
11
11
0
1
R/W
R/W
10
10
0
1
R/W
R/W
9
0
9
1
R/W
R/W
8
0
8
1
R/W
R/W
7
0
7
1
R/W
R/W
6
0
6
1
R/W
R/W
5
0
5
1
R/W
R/W
4
0
4
1
R/W
R/W
3
0
3
1
R/W
R/W
2
0
2
1
R/W
R/W
1
0
1
1
R/W
R/W
0
0
0
1