DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 222

no-image

DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 6 Interrupt Controller (INTC)
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
interrupt exception service routine.
(2)
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt exception service routine, execute the RTE instruction to return from interrupt exception
service routine.
Rev. 3.00 Sep. 28, 2009 Page 190 of 1650
REJ09B0313-0300
IRQ
Instruction (instruction replacing
interrupt exception handling)
Overrun fetch
First instruction in interrupt exception
service routine
[Legend]
m1:
m2:
m3:
Restoration from Bank
Vector address read
Saving of SR (stack)
Saving of PC (stack)
2 Icyc + 3 Bcyc + 1 Pcyc
Figure 6.12 Bank Save Timing
F
D
F
3 Icyc
3 Icyc + m1 + m2
E
Saved to bank
E
(1) VTO, PR, GBR, MACL
m1
M
(2) R12, R13, R14, MACH
m2
M
(3) R8, R9, R10, R11
m3
M
F
(4) R4, R5, R6, R7
E
D
(5) R0, R1, R2, R3
E

Related parts for DS72030W200FPV