DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 820

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
Synchronization
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where: M: Receive margin (%)
From equation 1, if F = 0, D = 0.5 and N = 16, the receive margin is 46.875%, as given by
equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 3.00 Sep. 28, 2009 Page 788 of 1650
REJ09B0313-0300
sampling timing
Data sampling
Receive data
Base clock
(RxD)
timing
M = (0.5 −
N: Ratio of clock frequency to bit rate (N = 16 or 8)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode
(Operation on a Base Clock with a Frequency 16 Times the Bit Rate)
0
1
2
8 clocks
Start bit
2N
3
1
4
) − (L − 0.5) F −
5
6
16 clocks
7
8
9 10 11 12 13 14 15
–7.5 clocks
D − 0.5
N
(1 + F) × 100 %
0
1
+7.5 clocks
2
3
4
D0
5
6
7
8
9
10 11 12 13 14 15
0
1
2
D1
3
4
5

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