DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 904

no-image

DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 17 I
Rev. 3.00 Sep. 28, 2009 Page 872 of 1650
REJ09B0313-0300
(a) SCL is normally driven
(c) When the rising speed of SCL is lowered
(b) When SCL is driven to low by the slave device
Internal SCL monitor
Internal SCL monitor
Internal SCL monitor
Synchronous clock
Synchronous clock
Synchronous clock
Notes: 1. The clock is the transfer rate clock set by the CKS[3:0] bits in the I
SCL pin
SCL pin
SCL pin
2
C Bus Interface 3 (IIC3)
2. When the NF2CYC bit in NF2CYC (NF2CYC) is set to 0, the internal delay time is 3 to 4 t
When this bit is set to 1, the internal delay time is 4 to 5 t
*
*
*
1
1
1
SCL
Time for
monitoring SCL
Time for
monitoring SCL
SCL is driven to low by
the slave device.
Internal
delay
Internal
delay
Figure 17.22 Bit Synchronous Circuit Timing
V
IH
Internal
delay
*
*
2
The monitor value
is low level.
2
V
V
IH
The monitor value is low level.
IH
The monitor value is
high level.
*
2
SCL is not driven to low.
SCL is not driven to low.
Time for
monitoring SCL
The monitor value
is high level.
pcyc
.
2
C bus control register 1 (ICCR1).
Time for
monitoring SCL
V
IH
Internal
delay
The monitor value
is high level.
pcyc
*
2
.
The frequency is not
the setting frequency.

Related parts for DS72030W200FPV