DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 171

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6
5.6.1
Exception handling can be triggered by trap instructions, slot illegal instructions, general illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
FPU exceptions
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
(including FPU instructions and
FPU-related CPU instructions in
FPU module standby state),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Undefined code anywhere
besides in a delay slot (including
FPU instructions and FPU-related
CPU instructions in FPU module
standby statute)
Division by zero
Negative maximum value ÷ (−1)
Starts when detecting invalid
operation exception defined by
IEEE754, division-by-zero
exception, overflow, underflow, or
inexact exception.
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
DIVU, DIVS
DIVS
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
Rev. 3.00 Sep. 28, 2009 Page 139 of 1650
Section 5 Exception Handling
REJ09B0313-0300