DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 81

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
Bit
31 to 15 —
14
13
12 to 10 —
9
8
7 to 4
3, 2
1
0
Global Base Register (GBR)
Vector Base Register (VBR)
Jump Table Base Register (TBR)
Bit Name Initial Value
BO
CS
M
Q
I[3:0]
—
S
T
All 0
0
0
All 0
—
—
1111
All 0
—
—
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or
fallen below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Specifies a saturation operation for a MAC
instruction.
T Bit
True/false condition or carry/borrow bit
Rev. 3.00 Sep. 28, 2009 Page 49 of 1650
REJ09B0313-0300
Section 2 CPU