DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 610

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(n)
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 11.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 11.56) immediately after the counters start operation, initial value output is not
suppressed.
Negative phase
Rev. 3.00 Sep. 28, 2009 Page 578 of 1650
REJ09B0313-0300
Positive phase
Counter start
TGRA_3
TGRB_3
Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Mode
H'0000
TCDR
TDDR
Tb interval
(1)
Figure 11.56 Timing for Synchronous Counter Clearing
(2)
(3)
(4)
Tb interval
(5)
(6)
(7)
(8)
(9)
Tb interval
(10) (11)
Output waveform is active-low
TCNT_3
TCNT_4

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