DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1471

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.3
The H-UDI has the following registers.
Table 29.2 Register Configuration
29.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
29.3.2
SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logic-
reset state, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not
guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Initial value:
Register Name
Bit
15 to 8
7 to 2
Bypass register
Instruction register
Note:
R/W:
Bit:
*
The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Register Descriptions
Bypass Register (SDBPR)
Instruction Register (SDIR)
Bit Name
TI[7:0]
⎯
15
1*
R
14
1*
R
13
1*
R
Initial
Value
11101111* R
All 1
12
0*
R
TI[7:0]
Abbreviation
SDBPR
SDIR
11
1*
R
10
R/W
R
1*
R
1*
R
9
Description
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 29.3.
Reserved
These bits are always read as 1.
R/W
⎯
R
1*
R
8
R
7
1
-
Initial Value
⎯
H'EFFD
Section 29 User Debugging Interface (H-UDI)
Rev. 3.00 Sep. 28, 2009 Page 1439 of 1650
R
6
1
-
R
5
1
-
R
4
1
-
Address
⎯
H'FFFE2000
R
3
1
-
R
2
1
-
REJ09B0313-0300
R
1
0
-
Access
Size
⎯
16
R
0
1
-