DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 276

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.3
9.3.1
In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled,
cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved
areas) according to the upper bits of the address.
External address spaces CS0 to CS7 are cache-enabled when internal address A29 = 0 or cache-
disabled when A29 = 1.
The kind of memory to be connected and the data bus width are specified in each partial space.
The address map for the external address space is listed below.
Table 9.2
Rev. 3.00 Sep. 28, 2009 Page 244 of 1650
REJ09B0313-0300
Internal Address
H'00000000 to H'03FFFFFF CS0
H'04000000 to H'07FFFFFF CS1
H'08000000 to H'0BFFFFFF CS2
H'0C000000 to H'0FFFFFFF CS3
H'10000000 to H'13FFFFFF CS4
H'14000000 to H'17FFFFFF CS5
H'18000000 to H'1BFFFFFF CS6
H'1C000000 to H'1FFFFFFF CS7
H'20000000 to H'23FFFFFF CS0
H'24000000 to H'27FFFFFF CS1
H'28000000 to H'2BFFFFFF CS2
H'2C000000 to H'2FFFFFFF CS3
H'30000000 to H'33FFFFFF CS4
H'34000000 to H'37FFFFFF CS5
H'38000000 to H'3BFFFFFF CS6
H'3C000000 to H'3FFFFFFF CS7
Area Overview
Address Map
Address Map
Space Memory to be Connected
Normal space, burst ROM (asynchronous or
synchronous)
Normal space, SRAM with byte selection
Normal space, SRAM with byte selection, SDRAM
Normal space, SRAM with byte selection, SDRAM
Normal space, SRAM with byte selection,
burst ROM (asynchronous)
Normal space, SRAM with byte selection, MPX-
I/O, PCMCIA
Normal space, SRAM with byte selection,
burst MPX-I/O, PCMCIA
Normal space, SRAM with byte selection
Normal space, burst ROM (asynchronous or
synchronous)
Normal space, SRAM with byte selection
Normal space, SRAM with byte selection, SDRAM
Normal space, SRAM with byte selection, SDRAM
Normal space, SRAM with byte selection,
burst ROM (asynchronous)
Normal space, SRAM with byte selection, MPX-
I/O, PCMCIA
Normal space, SRAM with byte selection,
burst MPX-I/O, PCMCIA
Normal space, SRAM with byte selection
Cache
Cache-enabled
Cache-disabled