DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1298

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 24 LCD Controller (LCDC)
Notes: Interrupt processing flow:
Rev. 3.00 Sep. 28, 2009 Page 1266 of 1650
REJ09B0313-0300
Bit
8
7 to 1
0
1. Interrupt signal is input
2. LDINTR is read
3. If MINTS, FINTS, VSINTS, or VEINTS is 1, a generated interrupt is memory access
4. If MINTS, FINTS, VSINTS, or VEINTS is 0, a generated interrupt is not memory access
5. UINTS is read.
6. If UINTS is 1, a generated interrupt is a user specified interrupt. Process for user
7. If UINTS is 0, a generated interrupt is not a user specified interrupt. Other processing is
Bit Name
UINTEN
⎯
UINTS
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt. Processing for each interrupt is performed.
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt.
specified interrupt is carried out.
performed.
Initial
Value
0
All 0
0
R/W
R/W
R
R/W
Description
User Specified Interrupt Enable
Sets whether generate an LCDC user specified
interrupt.
0: LCDC user specified interrupt is not generated
1: LCDC user specified interrupt is generated
Reserved.
These bits are always read as 0. The write value should
always be 0.
User Specified Interrupt State
This bit is set to 1 at the time an LCDC user specified
interrupt is generated (set state). During the user
specified interrupt handling routine, this bit should be
cleared by writing 0 to it.
0: LCDC did not generate a user specified interrupt or
1: LCDC has generated a user specified interrupt and
has been informed that the generated user specified
interrupt has completed
has not yet been notified that the generated user
specified interrupt has completed