DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 389

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(13) Low-Power SDRAM
The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.
The differences between the low-power SDRAM and normal SDRAM are that partial refresh
takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh
function, and that power consumption is low during refresh under user conditions such as the
operating temperature. The partial refresh is effective in systems in which there is data in a work
area other than the specific area can be lost without severe repercussions.
The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode
registers as the normal SDRAM. This LSI supports issuing of the EMRS command.
The EMRS command is issued according to the conditions specified in table below. For example,
if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued
to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the
MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data
H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the
CS3 space in the following sequence: PALL -> MRS -> EMRS.
Table 9.19 Output Addresses when EMRS Command Is Issued
Command to be
Issued
CS2 MRS
CS3 MRS
CS2 MRS + EMRS
(with refresh)
CS3 MRS + EMRS
(with refresh)
CS2 MRS + EMRS
(without refresh)
CS3 MRS + EMRS
(without refresh)
Access
Address
H'FFFC4XX0
H'FFFC5XX0
H'FFFC4XX0
H'FFFC5XX0
H'FFFC4XX0
H'FFFC5XX0
H'********
H'********
H'0YYYYYYY 32 bits
H'0YYYYYYY 32 bits
H'1YYYYYYY 32 bits
H'1YYYYYYY 32 bits
Access Data
Write
Access
Size
16 bits
16 bits
Rev. 3.00 Sep. 28, 2009 Page 357 of 1650
Section 9 Bus State Controller (BSC)
MRS
Command
Issue Address
H'0000XX0
H'0000XX0
H'0000XX0
H'0000XX0
H'0000XX0
H'0000XX0
H'YYYYYYY
H'YYYYYYY
H'YYYYYYY
H'YYYYYYY
EMRS
Command
Issue Address
⎯
⎯
REJ09B0313-0300