DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 248

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 7 User Break Controller (UBC)
(3)
(Example 3-1)
• Register specifications
Rev. 3.00 Sep. 28, 2009 Page 216 of 1650
REJ09B0313-0300
BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0194, BAR_1= H'00055555,
BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F,
BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: Internal CPU bus/instruction fetch/read (operand size is not included in the
condition)
<Channel 1>
Address:
Data:
Bus cycle: Internal DMA bus/data access/write/byte
On channel 0, the setting of the internal CPU bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data H'7x in address
H'00055555 on the internal DMA bus (access via the internal CPU bus does not generate a
user break).
Break Condition Specified for I Bus Data Access Cycle
H'00314156, Address mask: H'00000000
H'00055555, Address mask: H'00000000
H'00000078, Data mask: H'0000000F

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