DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 450

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.3.9
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the source of the DMA transfer request from peripheral modules in each channel.
DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4
and 5, and DMARS3 is for channels 6 and 7. Table 10.4 shows the specifiable combinations.
DMARS can specify the following transfer request sources: eight SCIF sources, eight IIC3
sources, one A/D converter source, five MTU2 sources, and two CMT sources, two USB sources,
two FLCTL sources, four SSI sources, four SSU sources.
Two RCAN-TL sources do not need to be specified by these registers, for these two sources can
be specified using the RS3 to RS0 bits in the DMA channel control register (CHCR).
• DMARS0
Initial value:
• DMARS1
Initial value:
• DMARS2
Initial value:
• DMARS3
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 418 of 1650
REJ09B0313-0300
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)
R/W
R/W
R/W
R/W
15
15
15
15
0
0
0
0
R/W
R/W
R/W
R/W
14
14
14
14
0
0
0
0
R/W
R/W
R/W
R/W
CH1 MID[5:0]
CH3 MID[5:0]
CH5 MID[5:0]
CH7 MID[5:0]
13
13
13
13
0
0
0
0
R/W
R/W
R/W
R/W
12
12
12
12
0
0
0
0
R/W
R/W
R/W
R/W
11
11
11
11
0
0
0
0
R/W
R/W
R/W
R/W
10
10
10
10
0
0
0
0
R/W
R/W
R/W
R/W
CH1 RID[1:0]
CH3 RID[1:0]
CH5 RID[1:0]
CH7 RID[1:0]
9
0
9
0
9
0
9
0
R/W
R/W
R/W
R/W
8
0
8
0
8
0
8
0
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
CH0 MID[5:0]
CH2 MID[5:0]
CH4 MID[5:0]
CH6 MID[5:0]
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
CH0 RID[1:0]
CH2 RID[1:0]
CH4 RID[1:0]
CH6 RID[1:0]
1
0
1
0
1
0
1
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0