DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 268

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8 Cache
(2)
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
Rev. 3.00 Sep. 28, 2009 Page 236 of 1650
REJ09B0313-0300
1. Instruction cache
1.1 Address array access
(a) Address specification
(b) Data specification (both read and write accesses)
1.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
[Legend]
*:
E:
X:
Read access
111100000
Write access
111100000
111100010
31
31
31
31
31
0 0 0
Data Array Write
Don't care
Bit 10 of entry address for read, don't care for write
0 for read, don't care for write
29 28
Figure 8.4 Specifying Address and Data for Memory-Mapped Cache Access
Tag address (28 to 11)
23 22
23 22
23 22
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
Longword data
W
W
W
11 10 9
10
E
Entry address
Entry address
Entry address
LRU
4
4
4
4
0
A
3
3
3
X
3
L
*
*
X
2
2
2
2
X
1
0
1
0
1
1
0
V
0
0
0
0
0
0
0
0
2. Operand cache
2.1 Address array access
(a) Address specification
(b) Data specification (both read and write accesses)
2.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
Read access
111100001
Write access
111100001
111100011
31
31
31
31
31
0 0 0
29 28
Tag address (28 to 11)
23 22
23 22
23 22
*----------*
*----------*
*----------*
13 12 11
13 12 11 10
13 12 11 10
W
W
W
11 10 9
Longword data
10
E
Entry address
Entry address
Entry address
LRU
4
4
4
4
0
A
3
3
3
X
3
L
X
2
*
2
*
2
2
0
0
U
0
1
1
1
1
V
0
0
0
0
0
0
0
0