DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 625

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(T3AEN and T4VEN are set to 1)
(4)
Complementary PWM mode output has the following protection function.
(a)
With the exception of the buffer registers, which can be rewritten at any time, access by the CPU
can be enabled or disabled for the mode registers, control registers, compare registers, and
counters used in complementary PWM mode by means of the RWE bit in the timer read/write
enable register (TRWER). The applicable registers are some (21 in total) of the registers in
channels 3 and 4 shown in the following:
• TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and
This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to
the mode registers, control registers, and counters. When the applicable registers are read in the
access-disabled state, undefined values are returned. Writing to these registers is ignored.
Note:
Buffer transfer-enabled period
Buffer transfer-enabled period
Buffer transfer-enabled period
TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3
and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR.
Figure 11.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer
Skipping counter 4VCNT
Complementary PWM Mode Output Protection Function
Register and counter miswrite prevention function
Skipping counter 3ACNT
The MD bits 3 to 0 = 1111 in TMDR_3, buffer transfer at the crest and the
trough is selected.
The skipping count is set to three.
T3AEN and T4VEN are set to 1.
(T3AEN is set to 1)
(T4VEN is set to 1)
0
0
1
Transfer-Enabled Period
1
2
2
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
3
3
0
Rev. 3.00 Sep. 28, 2009 Page 593 of 1650
0
1
1
2
REJ09B0313-0300
2
3
3
0