DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 833

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16.3.5
SSSR is a status flag register for interrupts.
Bit
7
6
5, 4
Bit Name
ORER
SS Status Register (SSSR)
Initial value:
Initial
Value
0
0
All 0
R/W:
Bit:
R/W
R
R/W
R
R
7
0
-
ORER
R/W
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either. Note
that this bit has no effect during slave data receive
operation (MSS in SSCRH cleared to 0 and TE and RE
in SSER set to 0 and 1, respectively) in SSU mode
(SSUMS in SSCRL cleared to 0).
[Setting condition]
[Clearing condition]
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
Section 16 Synchronous Serial Communication Unit (SSU)
When one byte of the next reception is completed
with RDRF = 1 (except during slave data reception
in SSU mode)
When writing 0 after reading ORER = 1
R
4
0
-
TEND
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 801 of 1650
TDRE
R/W
2
1
RDRF
R/W
1
0
R/W
CE
0
0
REJ09B0313-0300

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