DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 384

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)

(10) Low-Frequency Mode

When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and

fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency.

Figure 9.30 shows the access timing in low-frequency mode. In this mode, commands, addresses,

and write data are output in synchronization with the falling edge of CKIO, which is half a cycle

delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a

cycle faster than the normal timing. This timing allows the hold time of commands, addresses,

write data, and read data to be extended.

If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of

commands, addresses, write data, and read data are not guaranteed. Take the operating frequency

and timing design into consideration when making the SLOW bit setting.

Rev. 3.00 Sep. 28, 2009 Page 352 of 1650

REJ09B0313-0300

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 9.30 Low-Frequency Mode Access Timing