DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 254

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8 Cache
8.2
The cache has the following registers.
Table 8.2
8.2.1
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode
or write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a
cache-enabled space should be accessed after reading the contents of CCR1.
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 222 of 1650
REJ09B0313-0300
Register Name
Cache control register 1
Cache control register 2
R/W:
R/W:
Bit:
Bit:
Register Descriptions
Cache Control Register 1 (CCR1)
31
15
R
R
0
0
-
-
Register Configuration
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
28
12
Abbreviation
CCR1
CCR2
R
R
0
0
-
-
R/W
ICF
27
11
R
0
0
-
26
10
R
R
0
0
-
-
R/W
25
R/W
R/W
R
R
0
9
0
-
-
R/W
ICE
24
R
0
8
0
-
Initial Value
H'00000000
H'00000000
23
R
R
0
7
0
-
-
22
R
R
0
6
0
-
-
21
R
R
0
5
0
-
-
Address
H'FFFC1000 32
H'FFFC1004 32
20
R
R
0
4
0
-
-
R/W
OCF
19
R
0
3
0
-
18
R
R
Access Size
0
2
0
-
-
R/W
WT
17
R
0
1
0
-
R/W
OCE
16
R
0
0
0
-