DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 322

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Rev. 3.00 Sep. 28, 2009 Page 290 of 1650
REJ09B0313-0300
Bit
15, 14
13
12
11
Bit Name
⎯
DEEP
SLOW
RFSH
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the low-
power SDRAM enters the deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Low-Frequency Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read
data from SDRAM. Setting this bit makes the hold time
for command, address, write and read data extended
for half cycle (output or read at the falling edge of
CKIO). This mode is suitable for SDRAM with low-
frequency clock.
0: Command, address, and write data for SDRAM is
1: Command, address, and write data for SDRAM is
Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
output at the rising edge of CKIO. Read data from
SDRAM is latched at the rising edge of CKIO.
output at the falling edge of CKIO. Read data from
SDRAM is latched at the falling edge of CKIO.