DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 438

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 406 of 1650
REJ09B0313-0300
Bit
18
17
16
Bit Name
HIE
AM
AL
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Half-End Interrupt Enable
Specifies whether to issue an interrupt request to the
CPU when the transfer count reaches half of the
DMATCR value that was specified before transfer
starts.
When the HIE bit is set to 1, the DMAC requests an
interrupt to the CPU when the HE bit becomes 1.
0: Disables an interrupt to be issued when DMATCR
1: Enables an interrupt to be issued when DMATCR
Acknowledge Mode
Specifies whether DACK and TEND are output in data
read cycle or in data write cycle in dual address mode.
In single address mode, DACK and TEND are always
output regardless of the specification by this bit.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: DACK and TEND output in read cycle (dual address
1: DACK and TEND output in write cycle (dual
Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
= (DMATCR set before transfer starts)/2
= (DMATCR set before transfer starts)/2
mode)
address mode)