DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 793

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1).
Initial value:
Bit
15 to 1
0
Note:
R/W:
Bit:
*
Only 0 can be written to clear the flag after 1 is read.
Bit Name
—
ORER
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
12
R
0
-
11
R
0
-
R/W
R
R/(W)* Overrun Error
10
R
0
-
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
1: An overrun error has occurred*
[Setting condition]
•
Notes:
R
9
0
-
ORER is cleared to 0 when the chip is a power-on
reset
ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
R
8
0
-
1. Clearing the RE bit to 0 in SCSCR does
2. The receive FIFO data register
R
7
0
-
not affect the ORER bit, which retains its
previous value.
(SCFRDR) retains the data before an
overrun error has occurred, and the next
received data is discarded. When the
ORER bit is set to 1, the SCIF cannot
continue the next serial reception.
Rev. 3.00 Sep. 28, 2009 Page 761 of 1650
R
6
0
-
R
5
0
-
R
4
0
-
2
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
0
-
R/(W)*
ORER
1
0
0