DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 22

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3 Register Descriptions ......................................................................................................... 794
16.4 Operation ........................................................................................................................... 808
16.5 SSU Interrupt Sources and DMAC .................................................................................... 830
16.6 Usage Note......................................................................................................................... 831
Section 17 I
17.1 Features.............................................................................................................................. 833
17.2 Input/Output Pins............................................................................................................... 835
17.3 Register Descriptions ......................................................................................................... 836
17.4 Operation ........................................................................................................................... 852
Rev. 3.00 Sep. 28, 2009 Page xx of xxx
REJ09B0313-0300
16.3.1 SS Control Register H (SSCRH) .......................................................................... 795
16.3.2 SS Control Register L (SSCRL) ........................................................................... 797
16.3.3 SS Mode Register (SSMR) ................................................................................... 798
16.3.4 SS Enable Register (SSER) .................................................................................. 799
16.3.5 SS Status Register (SSSR) .................................................................................... 801
16.3.6 SS Control Register 2 (SSCR2) ............................................................................ 804
16.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 805
16.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 806
16.3.9 SS Shift Register (SSTRSR)................................................................................. 807
16.4.1 Transfer Clock ...................................................................................................... 808
16.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 808
16.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 809
16.4.4 Communication Modes and Pin Functions ........................................................... 811
16.4.5 SSU Mode............................................................................................................. 813
16.4.6 SCS Pin Control and Conflict Error...................................................................... 822
16.4.7 Clock Synchronous Communication Mode .......................................................... 823
16.6.1 Module Standby Mode Setting ............................................................................. 831
16.6.2 Note on Continuous Transmission/Reception in SSU Slave Mode ...................... 831
16.6.3 Note in the Master Transmission Operation or the Master Transmission/
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR).............................................................................. 849
17.3.7 I
17.3.8 I
17.3.9 I
17.3.10 NF2CYC Register (NF2CYC) .............................................................................. 851
Reception Operation of SSU Mode ...................................................................... 831
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1)..................................................................... 837
C Bus Control Register 2 (ICCR2)..................................................................... 840
C Bus Mode Register (ICMR)............................................................................ 842
C Bus Interrupt Enable Register (ICIER) ........................................................... 844
C Bus Status Register (ICSR)............................................................................. 846
C Bus Transmit Data Register (ICDRT) ............................................................ 849
C Bus Receive Data Register (ICDRR).............................................................. 850
C Bus Shift Register (ICDRS)............................................................................ 850
C Bus Interface 3 (IIC3)................................................................833