DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 774

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 742 of 1650
REJ09B0313-0300
Bit
1
Bit Name
RDF
Initial
Value
0
R/W
R/(W)* Receive FIFO Data Full
Description
Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the
quantity of data in SCFRDR has become more than
the receive trigger number specified by the RTRG[1:0]
bits in the FIFO control register (SCFCR).
0: The quantity of transmit data written to SCFRDR is
[Clearing conditions]
•
•
•
1: The quantity of receive data in SCFRDR is more
[Setting condition]
•
Note:
less than the specified receive trigger number
than the specified receive trigger number
RDF is cleared to 0 by a power-on reset, standby
mode
RDF is cleared to 0 when the SCFRDR is read
until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number after 1 is read from RDF and then 0 is
written
RDF is cleared to 0 when DMAC is activated by
receive FIFO data full interrupt (RXI) and read
SCFRDR until the quantity of receive data in
SCFRDR becomes less than the specified receive
trigger number
RDF is set to 1 when a quantity of receive data
more than the specified receive trigger number is
stored in SCFRDR*
*
As SCFTDR is a 16-byte FIFO register,
the maximum quantity of data that can be
read when RDF is 1 becomes the
specified receive trigger number. If an
attempt is made to read after all the data
in SCFRDR has been read, the data is
undefined. The quantity of receive data in
SCFRDR is indicated by the lower 8 bits
of SCFDR.