DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 858

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 16 Synchronous Serial Communication Unit (SSU)
(3)
Figure 16.15 shows an example of reception operation, and figure 16.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an SSRXI interrupt is generated. The
RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (SSERI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Rev. 3.00 Sep. 28, 2009 Page 826 of 1650
REJ09B0313-0300
User operation
LSI operation
Data Reception
RDRF
SSCK
SSO
Dummy-read SSRDR
Bit 0
Figure 16.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
1 frame
Bit 7
SSRXI interrupt
generated
Bit 0
Read data from SSRDR
1 frame
SSRXI interrupt
generated
Bit 7
Bit 0
Read data from SSRDR
SSRXI interrupt
generated
Bit 7

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