DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 491

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of five TCR registers, one each for channels 0 to 4. TCR register
settings should be conducted only when TCNT operation is stopped.
[Legend]
x:
Bit
7 to 5
4, 3
2 to 0
Don't care
Bit Name
CCLR[2:0]
CKEG[1:0]
TPSC[2:0]
Timer Control Register (TCR)
Initial value:
Initial
Value
000
00
000
R/W:
Bit:
R/W
7
0
R/W
R/W
R/W
R/W
CCLR[2:0]
R/W
6
0
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 11.4 and 11.5 for details.
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = Pφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is Pφ/4 or slower. When
Pφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 11.6 to 11.9 for details.
R/W
5
0
R/W
CKEG[1:0]
4
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 459 of 1650
R/W
2
0
TPSC[2:0]
R/W
1
0
R/W
0
0
REJ09B0313-0300