DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 786

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.8 Maximum Bit Rates with External Clock Input
15.3.9
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 754 of 1650
REJ09B0313-0300
Pφ (MHz)
8
16
24
28.7
30
33
Bit
15 to 11
R/W:
Bit:
FIFO Control Register (SCFCR)
Bit Name
15
R
0
-
(Clock Synchronous Mode, t
14
R
0
-
13
R
0
-
Initial
Value
All 0
12
R
0
-
External Input Clock (MHz)
0.6666
1.3333
2.0000
2.3916
2.5000
2.7500
11
R
0
-
R/W
R
R/W
10
0
RSTRG[2:0]
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Scyc
R/W
9
0
= 12t
R/W
8
0
pcyc
)
R/W
7
0
RTRG[1:0]
R/W
6
0
Maximum Bit Rate (bits/s)
666666.6
1333333.3
2000000.0
2391666.6
2500000.0
2750000.0
R/W
5
0
TTRG[1:0]
R/W
4
0
R/W
MCE
3
0
TFRST RFRST
R/W
2
0
R/W
1
0
LOOP
R/W
0
0

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