DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1447

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.2.10 Deep Standby Control Register (DSCTR)
DSCTR is an 8-bit readable/writable register that selects whether to retain the contents of the
corresponding area of the on-chip RAM (for data retention) in deep standby mode. Only byte
access is valid.
When the RRAMKP3 to 0 bits are set to 1, the contents of the corresponding area of the on-chip
RAM (for data retention) are retained in deep standby mode. When these bits are cleared to 0, the
contents of the corresponding area of the on-chip RAM (for data retention) are not retained in
deep standby mode.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit
7 to 4
3
2
Bit Name
⎯
RRAMKP3
RRAMKP2
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
On-Chip RAM Storage Area 3 (corresponding area of
on-chip RAM (for data retention): page 3*)
0: The contents of the corresponding on-chip RAM
1: The contents of the corresponding on-chip RAM
On-Chip RAM Storage Area 2 (corresponding area of
on-chip RAM (for data retention): page 2*)
0: The contents of the corresponding on-chip RAM
1: The contents of the corresponding on-chip RAM
R
5
0
-
(for data retention) area are not retained in deep
standby mode.
(for data retention) area are retained in deep
standby mode.
(for data retention) area are not retained in deep
standby mode.
(for data retention) area are retained in deep
standby mode.
R
4
0
-
RRAM
R/W
KP3
3
0
Rev. 3.00 Sep. 28, 2009 Page 1415 of 1650
RRAM
R/W
KP2
2
0
RRAM
R/W
KP1
1
0
Section 28 Power-Down Modes
RRAM
R/W
KP0
0
0
REJ09B0313-0300