DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 221

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.8.1
(1)
The contents of the general registers (R0 to R14), global base register (GBR), multiply and
accumulate registers (MACH and MACL), and procedure register (PR), and the vector table
address offset are banked.
(2)
This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in last-
out (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes
place in the reverse order, beginning from the last bank saved to.
6.8.2
(1)
Figure 6.11 shows register bank save operations. The following operations are performed when an
interrupt for which usage of register banks is allowed is accepted by the CPU:
a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the
b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector
c. The BN value is incremented by 1.
interrupt is generated.
table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN,
bank i.
Banked Register
Input/Output of Banks
Saving to Bank
Banked Register and Input/Output of Banks
Bank Save and Restore Operations
(c)
BN
+1
Figure 6.11 Bank Save Operations
(a)
Register banks
Bank i + 1
Bank 14
Bank 0
Bank 1
Bank i
:
:
:
:
(b)
Rev. 3.00 Sep. 28, 2009 Page 189 of 1650
Section 6 Interrupt Controller (INTC)
Registers
R0 to R14
MACH
MACL
GBR
VTO
PR
REJ09B0313-0300