DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 654

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.11 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.106 shows the timing in this case.
11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection
With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs
during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T
write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this
point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued.
Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0,
TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input
capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture
operation. The timing is shown in figure 11.107.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
Rev. 3.00 Sep. 28, 2009 Page 622 of 1650
REJ09B0313-0300
Figure 11.106 Contention between Buffer Register Write and Input Capture
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer register
Buffer register write cycle
M
Buffer register
T1
address
N
T2
M
N
2
state of the TCNT_2

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