DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 898

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 17 I
17.4.8
Flowcharts in respective modes that use the I
17.21.
Rev. 3.00 Sep. 28, 2009 Page 866 of 1650
REJ09B0313-0300
Example of Use
No
2
C Bus Interface 3 (IIC3)
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Read ACKBR in ICIER
Read BBSY in ICCR2
Read TEND in ICSR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Write transmit data
Set MST and TRS
Set MST and TRS
Write 1 to BBSY
Write 0 to BBSY
in ICCR1 to 0
Figure 17.18 Sample Flowchart for Master Transmit Mode
in ICCR1 to 1
and 0 to SCP
ACKBR=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
BBSY=0 ?
Last byte?
in ICDRT
Transmit
and SCP
Initialize
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear the STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
Test the status of the SCL and SDA lines.
Set master transmit mode.
Issue the start condition.
Set the first byte (slave address + R/W) of transmit data.
Wait for 1 byte to be transmitted.
Test the acknowledge transferred from the specified slave device.
Set the second and subsequent bytes (except for the final byte) of transmit data.
Wait for ICDRT empty.
Set the last byte of transmit data.
2
C bus interface 3 are shown in figures 17.18 to