DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1068

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 20 A/D Converter (ADC)
20.4.4
The A/D converter can be independently activated by an external trigger or an A/D conversion
request from the MTU2. To activate the A/D converter by an external trigger or the MTU2, set the
A/D trigger enable bits (TRGS[3:0]). When an external trigger or an A/D conversion request from
the MTU2 is generated with this bit setting, the ADST bit is set to 1 to start A/D conversion. The
channel combination is determined by bits CH2 to CH0 in ADCSR. The timing from setting of the
ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by
software.
20.4.5
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at the A/D conversion start delay time (t
starts conversion. Figure 20.5 shows the A/D conversion timing. Table 20.4 indicates the A/D
conversion time.
As indicated in figure 20.5, the A/D conversion time (t
time(t
conversion time therefore varies within the ranges indicated in table 20.4.
In multi mode and scan mode, the values given in table 20.4 apply to the first conversion. In the
second and subsequent conversions, time is the values given in table 20.5.
Rev. 3.00 Sep. 28, 2009 Page 1036 of 1650
REJ09B0313-0300
SPL
). The length of t
A/D Converter Activation by External Trigger or MTU2
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total
D
) after the ADST bit in ADCSR is set to 1, then
CONV
) includes t
D
and the input sampling