DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 411

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The burst ROM (clocked synchronous) interface is supported to access a ROM with a

synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the

same way as a normal space. This interface is valid only for area 0.

In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be

inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the

number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR.

While the burst ROM (clocked synchronous) is accessed, the BS signal is asserted only for the

first access cycle and an external wait input is also valid for the first access cycle.

If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the

burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width

for the burst ROM.

The burst ROM interface performs burst operations for all read access. For example, in a

longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is

read six times. These invalid data read cycles increase the memory access time and degrade the

program execution speed and DMA transfer speed. To prevent this problem, it is recommended

using a 16-byte read by cache fill in the cache-enabled spaces or 16-byte read by the DMA. The

burst ROM interface performs write access in the same way as normal space access.

Note: * The waveform for DACKn is when active low is specified.

Burst ROM (Clocked Synchronous) Interface

Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)

Figure 9.52 Burst ROM Access Timing (Clocked Synchronous)

(Burst Length = 8, Wait Cycles Inserted in First Access = 2,

Rev. 3.00 Sep. 28, 2009 Page 379 of 1650

Section 9 Bus State Controller (BSC)

REJ09B0313-0300