DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 985

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 11 — Timer Compare Match Interrupt 2 (IRR11): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the
TCMR2 matches to Cycle Time (TCMR2 = CYCTR), this bit is set.
Bit 10 — Start of new system matrix Interrupt (IRR10): Indicates that a new system matrix is
starting.
When CCR = 0, this bit is set at the successful completion of reception/transmission of time
reference message. Please note that when CMAX = 0 this interrupt is set at every basic cycle.
Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has
been received but the existing message in the matching Mailbox has not been read as the
corresponding RXPR or RFPR is already set to ‘1’ and not yet cleared by the CPU. The received
message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message
Control) bit. This bit is cleared when
(by writing ‘1’) or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set
cleared by writing a ‘1’ to all the correspondent bit position in MBIMR. Writing to this bit
position has no effect.
Bit 11: IRR11
0
1
Bit 10: IRR10
0
1
Description
Timer Compare Match has not occurred to the TCMR2 (initial value)
[Clearing condition] Writing 1
Timer Compare Match has occurred to the TCMR2
[Setting condition] TCMR2 matches to Cycle Time (TCMR2 = CYCTR)
Description
A new system matrix is not starting (initial value)
[Clearing condition] Writing 1
Cycle counter reached zero.
[Setting condition]
Reception/transmission of time reference message is successfully completed
when CMAX!= 3'b111 and CCR = 0
all bit in UMSR
(Unread Message Status Register)
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 953 of 1650
REJ09B0313-0300
. It is also
are cleared