DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 133

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3.3
Note: No FPU error occurs in the SH2A-FPU.
3.3.3
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
Bit
17 to 12
11 to 7
6 to 2
1
0
Field Name
Cause
Enable
Flag
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Floating-Point Communication Register (FPUL)
FPU exception
cause field
FPU exception
enable field
FPU exception flag
field
Bit Name
Cause
Enable
Flag
RM1
RM0
Bit Allocation for FPU Exception Handling
Initial
Value
All 0
All 0
All 0
0
1
FPU
Error (E)
Bit 17
None
None
R/W
R/W
R/W
R/W
R/W
R/W
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
The FPU exception source field is initially cleared to 0
when a floating-point operation instruction is executed.
When an FPU exception is generated by a floating-
point operation, the corresponding bits in the FPU
exception source field and FPU exception flag field are
set to 1. The FPU exception flag field bit remains set to
1 until it is cleared to 0 by software. FPU exception
handling occurs if the corresponding bit in the FPU
exception enable field is set to 1.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
Rev. 3.00 Sep. 28, 2009 Page 101 of 1650
Section 3 Floating-Point Unit (FPU)
Overflow
(O)
Bit 14
Bit 9
Bit 4
Underflow
(U)
Bit 13
Bit 8
Bit 3
REJ09B0313-0300
Inexact
(I)
Bit 12
Bit 7
Bit 2