DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 914

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 18 Serial Sound Interface (SSI)
Rev. 3.00 Sep. 28, 2009 Page 882 of 1650
REJ09B0313-0300
Bit
15
14
13
12
Bit Name
SCKD
SWSD
SCKP
SWSP
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Serial Bit Clock Direction
0: Serial bit clock is input, slave mode.
1: Serial bit clock is output, master mode.
Note: Only the following setting is allowed: (SCKD,
Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: Only the following setting is allowed: (SCKD,
Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
1: SSIWS and SSIDATA change at the SSISCK rising
SSIDATA input sampling
timing at the time of reception
(TRMD = 0)
SSIDATA output change
timing at the time of transmission
(TRMD = 1)
SSIWS input sampling timing at
the time of slave mode
(SWSD = 0)
SSIWS output change timing at
the time of master mode
(SWSD = 1)
Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
edge (sampled at the SCK rising edge).
edge (sampled at the SCK falling edge).
SWSD) = (0,0) and (1,1). Other settings are
prohibited.
SWSD) = (0,0) and (1,1). Other settings are
prohibited.
SSISCK rising edge
SSISCK falling edge SSISCK rising edge
SSISCK rising edge
SSISCK falling edge
SCKP = 0
SSISCK falling edge
SSISCK falling edge
SSISCK rising edge
SCKP = 1

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