DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1157

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.11 Interrupts Enable Register 0 (INTENB0)
INTENB0 is a register that specifies the interrupt masks. The URST, SADR, SCFG and SUSP bits
operate as interrupt mask bits for the device state transition interrupt sources. The WDST, RDST,
CMPL and SERR bits operate as interrupt mask bits for the control transfer stage interrupt
sources.
This register is initialized by a power-on reset or a software reset.
Initial value:
Bit
15
14
13
12
11
10
R/W:
Bit:
VBSE
R/W
Bit Name
VBSE
RSME
SOFE
DVSE
CTRE
BEMPE
15
0
RSME SOFE
R/W
14
0
R/W
13
0
Initial
Value
0
0
0
0
0
0
DVSE
R/W
12
0
CTRE BEMPE NRDYE BRDYE URST
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10
0
R/W
9
0
Description
VBUS Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Resume Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Frame Number Update Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Device State Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Control Transfer Stage Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Buffer Empty Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
R/W
8
0
Section 23 USB 2.0 Host/Function Module (USB)
R/W
7
0
Rev. 3.00 Sep. 28, 2009 Page 1125 of 1650
SADR
R/W
6
0
SCFG
R/W
5
0
SUSP WDST RDST
R/W
4
0
R/W
3
0
REJ09B0313-0300
R/W
2
0
CMPL
R/W
1
0
SERR
R/W
0
0