DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 393

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note:
Bus Width
32 bits
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
* When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
D31 to D0
A25 to A0
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
DACKn*
RD/WR
WAIT
CKIO
Figure 9.35 Burst ROM Access Timing (Clocked Asynchronous)
CSn
Access Size
8 bits
16 bits
32 bits
16 bytes
RD
BS
Note: * The waveform for DACKn is when active low is specified.
T1
Tw
CSnWCR. BST[1:0] Bits Number of Bursts Access Count
Not affected
Not affected
Not affected
Not affected
Tw
T2B
Twb
T2B
1
1
1
4
Rev. 3.00 Sep. 28, 2009 Page 361 of 1650
Twb
Section 9 Bus State Controller (BSC)
T2B
Twb
T2
1
1
1
1
REJ09B0313-0300

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