DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1470

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 29 User Debugging Interface (H-UDI)
29.2
Table 29.1 Pin Configuration
Note:
Rev. 3.00 Sep. 28, 2009 Page 1438 of 1650
REJ09B0313-0300
Pin Name
Clock pin for H-UDI serial data
I/O
Mode select input pin
H-UDI reset input pin
H-UDI serial data input pin
H-UDI serial data output pin
ASE mode select pin
* When the emulator is not in use, fix this pin to the high level.
Input/Output Pins
TMS
TDI
Symbol
TCK
TRST
TDO
ASEMD*
I/O
Input
Input
Input
Input
Output
Input
Function
Data is serially supplied to the H-UDI from
the data input pin (TDI), and output from
the data output pin (TDO), in
synchronization with this clock.
The state of the TAP control circuit is
determined by changing this signal in
synchronization with TCK. For the protocol,
see figure 29.2.
Input is accepted asynchronously with
respect to TCK, and when low, the H-UDI is
reset. TRST must be low for a constant
period when power is turned on regardless
of using the H-UDI function. See section
29.4.2, Reset Configuration, for more
information.
Data transfer to the H-UDI is executed by
changing this signal in synchronization with
TCK.
Data read from the H-UDI is executed by
reading this pin in synchronization with
TCK. The initial value of the data output
timing is the TCK falling edge. This can be
changed to the TCK rising edge by
inputting the TDO change timing switch
command to SDIR. See section 29.4.3,
TDO Output Timing, for more information.
If a low level is input at the ASEMD pin
while the RES pin is asserted, ASE mode is
entered; if a high level is input, product chip
mode is entered. In ASE mode, dedicated
emulator function can be used. The input
level at the ASEMD pin should be held for
at least one cycle after RES negation.