DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 851

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Hatching boxes represent SSU internal operations.
[1]
[2]
[4]
[5]
[6]
No
Read received data in SSRDR
Read receive data in SSRDR
Consecutive data reception?
Clear the ORER bit in SSSR
RDRF automatically cleared
Overrun error processing
Dummy-read SSRDR
Figure 16.8 Flowchart Example of Data Reception (SSU Mode)
End reception
End reception
Initial setting
Read SSSR
ORER = 1?
RDRF = 1?
RE = 0
Start
Yes
Yes
No
Yes
No
[3]
[1]
[2]
[3], [6] Receive error processing:
[4]
[5]
Section 16 Synchronous Serial Communication Unit (SSU)
Initial setting:
Specify the receive data format.
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
reception is not resumed.
To continue single reception:
When continuing single reception, wait for time of t
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
Rev. 3.00 Sep. 28, 2009 Page 819 of 1650
REJ09B0313-0300
SUcyc