DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 92

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 60 of 1650
REJ09B0313-0300
Addressing
Mode
Indexed GBR
indirect
TBR duplicate
indirect with
displacement
PC indirect with
displacement
Instruction
Format
@(R0, GBR) The effective address is the sum of GBR value
@@
(disp:8,
TBR)
@(disp:8,
PC)
Effective Address Calculation
and R0.
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
The effective address is the sum of PC value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
(zero-extended)
(zero-extended)
H'FFFFFFFC
GBR
R0
disp
disp
TBR
PC
2/4
4
×
&
×
+
+
(for longword)
+
PC & H'FFFFFFFC
GBR + R0
+ disp × 4)
PC + disp × 2
+ disp × 4
+ disp × 4
(TBR
TBR
or
Equation
GBR + R0
Contents of
address (TBR
+ disp × 4)
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC +
disp × 4

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