DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 262

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8 Cache
8.3.2
(1)
In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way
is the latest.
(2)
An external bus cycle starts and the entry is updated. The way replaced follows table 8.4. Entries
are updated in 16-byte units. When the desired data that caused the miss is loaded from external
memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.
When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way
becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the
entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts
after the entry is transferred to the write-back buffer. After the cache completes its update cycle,
the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. Cache
updates and write-backs to memory are performed in wrap-around fashion. For example, if the
value of the lower four bits of an address that triggers a read miss is H'4, the value of the lower
four address bits changes from H'4 to H'8, H'C, and H'0, in that order, when cache updates or
write-backs are performed.
8.3.3
(1)
LRU is updated so that the hit way becomes the latest. The contents in other caches are not
modified. No data is transferred to the CPU.
(2)
No data is transferred to the CPU. The way to be replaced follows table 8.3. Other operations are
the same in case of read miss.
Rev. 3.00 Sep. 28, 2009 Page 230 of 1650
REJ09B0313-0300
Read Hit
Read Miss
Prefetch Hit
Prefetch Miss
Read Access
Prefetch Operation (Only for Operand Cache)