DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1261

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

This section describes the transfer scheduling within a frame of this module. After the module

sends an SOF, the transfer is carried out in the sequence described below.

1. Execution of periodic transfers

2. Setup transactions for control transfers

3. Execution of bulk and control transfer data stages and status stages

Setting the UACT bit of the DVSTCTR register to 1 initiates sending of an SOF or μSOF, and

makes it possible to generate a transaction.

Setting the UACT bit to 0 stops the sending of the SOF or μSOF and initiates a suspend state. If

the setting of the UACT bit is changed from 1 to 0, processing stops after the next SOF or μSOF is

A pipe is searched in the order of Pipe 1 → Pipe 2 → Pipe 6 → Pipe 7, and then, if the pipe is

one for which an isochronous or interrupt transfer transaction can be generated, the transaction

is generated.

The DCP is checked, and if a setup transaction is possible, it is sent.

A pipe is searched in the order of DCP → Pipe 1 → Pipe 2 → Pipe 3 → Pipe 4 → Pipe 5, and

then, if the pipe is one for which a bulk or control transfer data stage or a control transfer status

stage transaction can be generated, the transaction is generated.

If a transfer is generated, processing moves to the next pipe transaction regardless of whether

the response from the peripheral is ACK or NAK. Also, if there is time for the transfer to be

done within the frame, step 3 is repeated.

Transfer Schedule

USB Communication Enabled

Section 23 USB 2.0 Host/Function Module (USB)

Rev. 3.00 Sep. 28, 2009 Page 1229 of 1650

REJ09B0313-0300