DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 845

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4.5
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1)
Figure 16.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
[1]
[2]
[3]
[4]
[5]
Initial Settings in SSU Mode
Clear the SSUMS bit in SSCRL to 0 and
Specify the MLS, CPOS, CPHS, CKS2,
Clear the TE and RE bits in SSER to 0
Set PFC for external pins to be used
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
and CEIE bits in SSER all together
CSS1, and CSS0 bits in SSCRH
specify bits DATS1 and DATS0
Specify TEIE, TIE, RIE, TE, RE
CKS1, and CKS0 bits in SSMR
SSU Mode
Specify the MSS, BIDE, SOL,
(SSCK, SSI, SSO, and SCS)
Start setting initial values
End
Figure 16.4 Example of Initial Settings in SSU Mode
[1] Make appropriate settings in the PFC for the external pins to be used.
[2] Specify master/slave mode selection, bidirectional mode enable,
[3] Selects SSU mode and specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock polarity selection,
[5] Enables/disables interrupt request to the CPU.
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
clock phase selection, and transfer clock rate selection.
Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Sep. 28, 2009 Page 813 of 1650
REJ09B0313-0300