DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 766

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 734 of 1650
REJ09B0313-0300
Bit
4
3
Bit Name
RE
REIE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Enable
Enables or disables the serial receiver.
0: Receiver disabled*
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note:
Receive Error Interrupt Enable
(BRI) requests are disabled
(BRI) requests are enabled*
2. Serial reception starts when a start bit is
*
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
detected in asynchronous mode, or
synchronous clock is detected in clock
synchronous mode. Select the receive format
in SCSMR and SCFCR and reset the receive
FIFO before setting RE to 1.
ERI or BRI interrupt requests can be
cleared by reading the ER, BR or ORER
flag after it has been set to 1, then clearing
the flag to 0, or by clearing RIE and REIE to
0. Even if RIE is set to 0, when REIE is set
to 1, ERI or BRI interrupt requests are
enabled. Set so If SCIF wants to inform
INTC of ERI or BRI interrupt requests
during DMA transfer.
2
1

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