DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 468

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
• Intermittent Mode 16 and Intermittent Mode 64
Rev. 3.00 Sep. 28, 2009 Page 436 of 1650
REJ09B0313-0300
⎯ Dual address mode
⎯ DREQ low level detection
In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next
transfer request occurs after that, DMAC obtains the bus mastership from other bus master
after waiting for 16 or 64 cycles of Bφ clock. DMAC then transfers data of one unit and returns
the bus mastership to other bus master. These operations are repeated until the transfer end
condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA
transfer than the normal mode of cycle steal.
When DMAC obtains again the bus mastership, DMA transfer may be postponed in case of
entry updating due to cache miss.
The cycle-steal intermittent mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in
all channels.
Figure 10.10 shows an example of DMA transfer timing in cycle-steal intermittent mode.
Transfer conditions shown in the figure are;
⎯ Dual address mode
⎯ DREQ low level detection
Bus cycle
DREQ
Figure 10.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode
Bus cycle
Figure 10.9 DMA Transfer Example in Cycle-Steal Normal Mode
CPU
DREQ
CPU
CPU
(Dual Address, DREQ Low Level Detection)
(Dual Address, DREQ Low Level Detection)
CPU DMAC DMAC CPU
CPU
Read/Write
CPU DMAC DMAC CPU
More than 16 or 64 Bφ clock cycles
(depending on the state of bus used by bus master such as CPU)
Bus mastership returned to CPU once
Read/Write
CPU DMAC DMAC CPU
DMAC DMAC CPU
Read/Write
Read/Write