DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 344
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 9 Bus State Controller (BSC)
9.5.5
MPX-I/O Interface
Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn
signals control the accessing. The basic access for the MPX space consists of 2 cycles of address
output followed by an access to a normal space. The bus width for the address output cycle or the
data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits
depending on the address to be accessed.
Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3.
Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided
without inserting idle cycles, even in continuous access cycles. Address output is increased to 3
cycles by setting the MPXW bit in CS5WCR to 1.
The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and
low in the write cycle.
The data cycle is the same as that in a normal space access.
Timing charts are shown in figures 9.11 to 9.13.
Rev. 3.00 Sep. 28, 2009 Page 312 of 1650
REJ09B0313-0300
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