DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1103

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.8
FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer
requests or interrupts. A transfer request from the FLCTL to the DMAC is issued after each access
mode has been started.
Bits 9 to 5 are the flag bits that indicate various errors occurred in flash memory access and
whether there is a transfer request from the FIFO. Only 0 can be written to these bits. To clear a
flag, write 0 to the target flag bit and 1 to the other flag bits.
Initial value:
Initial value:
Bit
31 to 25
24
23, 22
Note:
R/W:
R/W:
Bit:
Bit:
*
Only 0 can be written to these bits.
Interrupt DMA Control Register (FLINTDMACR)
31
15
Bit Name
—
ECERINTE 0
—
R
R
0
0
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
All 0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R
R/W
R
26
10
R
R
0
0
-
-
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
ECC Error Interrupt Enable
0: Disables an interrupt when an ECC error occurs
1: Enables an interrupt when an ECC error occurs
Reserved
These bits are always read as 0. The write value should
always be 0.
ERB
25
EC
R
0
9
0
-
Section 22 AND/NAND Flash Memory Controller (FLCTL)
ECER
INTE
R/W
ERB
24
ST
0
8
0
BTO
ERB
23
R
0
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1071 of 1650
EQF1
TRR
22
R
0
6
0
-
EQF0
R/W
TRR
21
0
5
0
FIFOTRG
[1:0]
STER
R/W
INTE
20
0
4
0
RBER
R/W
R/W
INTE
CLR
AC1
19
0
3
0
REJ09B0313-0300
R/W
R/W
INTE
CLR
AC0
18
TE
0
2
0
DREQ1
INTE1
R/W
R/W
17
EN
TR
0
1
0
DREQ0
INTE0
R/W
R/W
16
EN
TR
0
0
0